• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Control system, particularly for an aircraft, of at least one power unit (5, 5b, 5n) able to open or close the connection between at least one source of electrical energy and at least one powered device, and means for measuring the state of the power supply path. The system comprises at least two microcontrollers (1a, 1b) each capable of transmitting a command to each power unit (5, 5b, 5n), and connected to at least a part of the means for measuring the state of the device. power supply path, and means for determining the command to be transmitted (14, 14b, 14n) able to determine the command to be transmitted to each power unit (5, 5b, 5n) among the commands issued by each microcontroller ( 1a, 1b) to said controller.
    公开号:FR3024925A1
    申请号:FR1457843
    申请日:2014-08-14
    公开日:2016-02-19
    发明作者:Jean-Clair Pradier；Stephane Guenot
    申请人:Zodiac Aero Electric SAS；
    IPC主号:
    专利说明:

    [0001] System and method for controlling at least one power unit, in particular for aircraft.
    [0002] The technical field of the invention is the control of electrical distribution systems, and more particularly the secure control of such systems. The invention relates to the use of a centralized control and protection architecture associated with a power electronics whose function is to convert electrical energy, statically or dynamically. The term Solid State Power Controller (SSPC) is used to describe static electric power distribution functions involving semiconductor-based components. These functions are split between SSPC and SSPC. The purpose of the SSPC channels is to distribute electrical energy to the aircraft loads based on logic signals from avionics related control means. The SSPC channels also have the role of protecting the lines that convey electrical energy to the loads of the aircraft. By charge of the aircraft is meant electrical equipment consuming the electric power provided. SSPCs complement the SSPC channels in the protection of distribution lines and are generally included in secondary power distribution equipment because of the average power transmitted. In addition, because of the average power transmitted by each power line, several SSPC channels can be grouped and controlled by an SSPC card. Each SSPC path first comprises a power unit, which operates to close or open the link between a power source and a load. The power unit comprises one or more semiconductor-based switches or transistors, in particular JFETs (junction field effect transistor), MOSFET (Metal-oxide gate field effect transistor), IGBT ( Isolated Grid Bipolar Transistor), Bipolar or Thyristor, etc. The manufacturing technologies of these semiconductors can be specific to different materials, such as in particular Si, SiC, GaN.
    [0003] The power unit is associated with one or more sensors, particularly current and voltage, to distinguish a nominal case of operation of a case of failure, including over-current, short circuit or arcing. electric. The SSPC channel is dynamically controlled and configured by the SSPC card in several aspects, including the current rating of the channel (current that the line will see in normal operating mode), the activation or not of each of the on-board protections. , the possibility of resetting a field indicating that the SSPC channel was commanded to open due to the occurrence of a fault. For all these reasons and because of the complexity of certain protection laws governing the behavior of the SSPC card, the latter is very often driven by a microcontroller. The microcontroller can, at the user's choice, be referenced from the point of view of the electrical mass of its electronics, that is to say at the level of the power bus, the microcontroller must therefore be isolated from the low functions. -levels of the SSPC map. In this case, the architecture is said to be isolated. Otherwise, it can be referenced to the electrical ground of low level functions of the SSPC board. In this case the architecture is said to be uninsulated. The SSPC card includes main functions, called low level, some examples of which are listed below. A general power function allows the supply of energy for the electronic functions of the card and the management of the transparency time. External communication functions are realized by means of interface blocks with discrete signals allowing the control of SSPC channels, pin programming, ie programming by pins and the return of information and 3024925 3 communication gateways to exchange, via digital data buses, information such as control, monitoring and embedded test type BITE (acronym for "Built-In Test Equipment") tracks SSPC.
    [0004] Measuring functions make it possible to determine the current flowing in the SSPC channel, as well as the voltage and temperature at the power unit. Limiting functions of the leakage current make it possible to compensate for the leakage current of the power unit.
    [0005] In the same manner, the main functions performed by each of the SSPC channels are as follows: - Low-voltage supply to generate the supply voltage for the following functions - Control electronics of the SSPC; 15 - Electronics for rapid detection of a short-circuit case; - Electronics for locking a fault of the short-circuit type; and - Voltage and current measurement functions. The microcontroller which manages the protections of the SSPC channel can be connected to a communication gateway or be a direct subscriber of an airplane communication bus. The SSPC path is generally, for reasons of availability, connected to at least two control members. Generally adopted architectures, isolated or not, use a SSPC microcontroller, as illustrated in FIG. 1. FIG. 1 presents the various possible galvanic isolations. A first isolation (3, 3b, 3n) is possible between the communication gateway and the microcontroller (1, lb, ln). A second isolation (5, 5b, 5n) is possible between the microcontroller and the SSPC channels (2, 2b, 2n). In the case of an isolated architecture, the first isolation (3, 3b, 3n) is implemented, while the second isolation is not (5, 5b, 5n) implemented. In the case of an uninsulated architecture, the second isolation (5.5b, 5n) is implemented, while the first isolation (3, 3b, 3n) is not implemented. Figures 2 and 3 illustrate isolated and non-isolated control / protection architectures of an SSPC path.
    [0006] FIG. 2 illustrates a galvanic isolation 3 arranged upstream of the microcontroller 1, the output of the microcontroller 1 being directly connected to the various means of control (6, 7, 8) and of monitoring 9 of the SSPC path, in particular to the organ The internal power supply is provided via a DC-DC converter 10 supplementing the galvanic isolation 11 separating the insulated area 12 from the non-insulated area 13. FIG. 3 illustrates a galvanic isolation 4 arranged downstream of the microcontroller 1, before connection to the various control means (6, 7, 8) and monitoring 9 of the SSPC channel, in particular to the power unit 5. However, a measurement means 9b directly links the microcontroller 1 to the distribution line controlled by the power unit 5. The internal power supply is provided via a DC-DC converter 10 completing the galvanic isolation 11 20 separating the isolated area 12 of the non-insulated area 13. The disadvantages of the architecture shown in Figure 1 are multiple. The greater the number of SSPC channels and the larger the area occupied by the protection functions, an SSPC channel corresponding to the use of a microcontroller dedicated to the protection of the line. This multiplicity of components is accompanied by an increase in the costs, the power dissipated and the implantation surface, to the detriment of the useful surface for the power parts of these same SSPC channels.
    [0007] The greater the number of SSPC channels, the lower the mean time to failure MTBF (acronym for "Mean Time Before Failure") of the SSPC card, the microcontroller and its peripherals being a very important contributor in the value of MTBF. an electronic card.
    [0008] Another disadvantage is the need to use additional microcontrollers dedicated to communication functions in addition to those providing line protection. The new existence of these microcontrollers is accompanied by an increase in the signals exchanged with the SSPC channel and consequently an increase in the complexity of the routing. An alternative is to subscribe the microcontroller of the SSPC channel directly on a bus. Unfortunately, by increasing the number of subscribers per bus, there is a risk of saturation of the data bus and a greater probability of bus loss. The multiplication of the microcontrollers also complicates the management of the communication with the communication gateway of the SSPC card. It is indeed not conceivable to process sequentially the passage of commands from the communication gateway to the microcontrollers managing the protection of SSPC channels, unless it is not constrained from the point of view of the reactivity of the SSPC card. In a three-phase configuration, it is necessary to share a link between the three microcontrollers associated with the same three-phase group, a requirement often formulated to open the three lines when a fault appears on one of the SSPC lines. . This requirement has the consequence, in the case of the use of several microcontrollers, either that the microcontrollers exchange 25 with each other or that they exchange with a common gateway. There is a need for a power organ control system and method for efficient and secure control with a smaller number of components than the state of the art.
    [0009] The subject of the invention is a control system, in particular for an aircraft, of at least one power unit able to open or close the connection between at least one source of electrical energy and at least one powered device, and means measuring the state of the power supply path. The system comprises at least two microcontrollers each capable of transmitting a command to each power unit of a power supply channel, and connected to at least a part of the measurement means of the state of the channel. power supply, and means for determining the command to be transmitted able to determine the command to be transmitted to each power unit among the commands issued by each microcontroller to said power unit. The means for determining the command to be transmitted may comprise three inputs bearing a control signal coming from three microcontrollers, the input bearing the control signal of a first microcontroller being connected to a logic gate NO, the input carrying the control signal of a second microcontroller and the input carrying the control signal of a third microcontroller being connected to a first AND logic gate, the logic gate AND and the first AND logic gate being connected to a second AND logic gate the input carrying the control signal of the second microcontroller and the input carrying the control signal of the third microcontroller being connected to a first OR logic gate, the input carrying the control signal of the first microcontroller and the first logic gate. OR being connected to a third AND logic gate, the second AND logic gate and the third AND logic gate being connected to a second OR logic gate, the output of the second OR logic gate being connected to the output of the means for determining the command to be transmitted.
    [0010] The means for determining the command to be transmitted may comprise four inputs connected two by two to two microcontrollers, the four inputs carrying two control signals each originating from a microcontroller, and two validity signals, each also originating from a microcontroller. the second microcontroller providing redundancy of the first microcontroller, the input carrying the control signal of the first microcontroller and the input bearing the validity signal of the first microcontroller being connected to a first logic gate NAND, 3024925 7 input carrying the control signal of the second microcontroller and the input bearing the validity signal of the second microcontroller being connected to a second NAND logic gate, the input bearing the validity signal of the first microcontroller and the second logic gate NO And being connected to an OR logic gate, the first logic gate NAND and the logic OR gate being connected to a third NAND logic gate, the output of the third NAND logic gate being connected to the output of the determination means of the command to be transmitted. The means for determining the command to be transmitted may comprise four inputs connected two by two to two microcontrollers, the four inputs carrying two control signals each originating from a microcontroller, and two signals of validity, each also originating from a microcontroller. the second microcontroller providing redundancy of the first microcontroller, the input carrying the control signal of the first microcontroller and the input bearing the validity signal of the first microcontroller are connected to a first logic gate NAND, the input carrying the control signal of the second microcontroller and the input bearing the validity signal of the second microcontroller are connected to a second NAND logic gate, the input carrying the validity signal of the first microcontroller and the second logic gate NAND are connected to a first OR logic gate, the first NAND logic gate and the first OR logic gate (21) are connected to a third NAND logic gate, the input carrying the control signal of the first microcontroller and the input carrying the control signal of the second microcontroller being connected to a second logic gate OR exclusive, the input carrying the validity signal of the first microcontroller and the input carrying the validity signal of the second microcontroller being connected to a fourth AND logic gate, the second exclusive OR logic gate and the fourth logic AND gate being connected to a fifth AND logic gate, the third NAND logic gate and the fifth AND logic gate being connected to a sixth NAND logic gate, the third NAND logic gate being connected to a logic gate NO, the logic gate NO and the fifth AND gate being connected to a seventh NAND logic gate, the sixth NAND logic gate being connected to the first input of an eighth NAND logic gate, the seventh NAND logic gate being connected to the second input of a ninth NAND logic gate, the output of the ninth NAND logic gate being connected to the second input of the eighth logic gate NAND, the output of the eighth NAND logic gate being connected to the first input of the ninth NAND logic gate, the output of the eighth NAND logic gate being also 20 connected to the output of the means for determining the command to be transmitted. The invention also relates to the use of the system described above and its variants, in an electrical distribution system of an aircraft comprising at least one electrical supply channel comprising at least one power unit. The invention furthermore relates to a control method, in particular for an aircraft, of a power unit able to open or close the connection between at least one source of electrical energy and at least one powered device, by means of a control system 30 comprising means for measuring the state of the connection, and at least two microcontrollers each able to transmit a command to each power unit, and connected to at least a part of the measuring means of the state of the connection.
    [0011] The method comprises a step during which the control transmitted to each power unit is determined among the commands issued by the microcontrollers to each power unit.
    [0012] It is possible to output a command corresponding to the command received from a majority of the microcontrollers, the control system comprising an odd number of microcontrollers greater than three. Each microcontroller can issue a command that can take a first value or a second value and a validity value that can take a first value if the command is judged valid by the microcontroller and a second value if the command is judged invalid by the microcontroller, a second microcontroller ensuring the redundancy of the first microcontroller. If the commands received as inputs are accompanied by different validity values, the command received at the input for which the validity value corresponds to the first value is transmitted, or if different commands received as entries are accompanied by corresponding validity values. at the second validity value, the first control value is transmitted, or, if identical commands received as inputs are accompanied by validity values corresponding to the second validity value, the first control value is transmitted. If different commands received as inputs are accompanied by validity values corresponding to the first value, the command transmitted by the first microcontroller can be transmitted. If different commands received as inputs are accompanied by validity values corresponding to the first value, the previously received command may be transmitted. The invention also relates to the use of the method described above and its variants for controlling the electrical distribution system of an aircraft comprising at least one power supply channel comprising at least one power unit . The invention defined above has many advantages. A first advantage lies in reducing the number of microcontrollers required which allows an increase in the usable area for the power parts, a reduction in the cost of the components, a decrease in the total power dissipated by the protection functions and an increase in the MTBF of the electronic card, the microcontroller and its peripherals being very important contributors in the MTBF value of an electronic card, more particularly of an SSPC card. A second advantage corresponds to the centralization of the protection and control functions in a single microcontroller, which makes it possible, in a three-phase configuration, to better manage the control of the SSPCs associated with the same three-phase group. Indeed, it is often required for security reasons to open the three phases to the appearance of a defect on one of the SSPC lines. Finally, another advantage arises because the microcontroller centralizing the protection functions can also act as gateway communication to the outside. In doing so, the internal communication buses between the protection microcontroller and the communication gateway are removed. Other objects, features and advantages of the invention will become apparent on reading the following description, given solely by way of nonlimiting example and with reference to the appended drawings, in which: FIG. 1 illustrates a general architecture of FIG. SSPC control and protection of channels, protection of an SSPC channel according to the invention, - Figure 2 illustrates an architecture of isolated control and protection of SSPC channels, - Figure 3 illustrates an architecture of control and protection not 4 illustrates a control architecture and FIG. 5 illustrates a first embodiment of a means for determining the control to be transmitted according to the invention, FIG. second embodiment of a means for determining the control to be transmitted according to the invention; FIG. 7 illustrates another architecture for controlling and protecting channels according to the invention; FIG. 8 illustrates a third embodiment of a means for determining the control to be transmitted according to the invention; FIG. 9 illustrates another architecture for controlling and protecting channels according to the invention integrating FPGAs. A centralized, uninsulated control and protection architecture associated with a power portion whose function is to distribute electrical energy, either statically or dynamically, is described below. The use of this new control and protection architecture is hereinafter described in the context of an SSPC application. However, it can be generalized to electrical distribution control devices. The capabilities of the current microcontrollers make it possible to consider having, in the same component, a large computing power. Due to technical developments in the field of microelectronics, the computing power of microprocessors is expected to grow in the future. Thus the use of a single microcontroller instead of several can be considered. This perspective gives rise to a new command and protection architecture illustrated in Figure 4 in a context of SSPC usage.
    [0013] The following description is made by considering microcontrollers. However, it can easily be generalized to any type of control means capable of transmitting the signals required at the output. In this architecture, a single microcontroller is associated with all or part of the SSPC channels of the SSPC card. An SSPC path is a particular example of a power supply path. The present description can be generalized to the case of a power supply path. Moreover, if the processing capabilities of the microcontroller 5 are insufficient, at least one additional microcontroller can be used so that the sum of the processing capabilities of the microcontrollers is greater than or equal to the processing capacity necessary to manage all the channels. SSPC. As explained above, each microcontroller can interface with a communication bus or be directly connected to an airplane bus. In addition, it sends the control commands to the control members (8, 8b, 8n) of the SSPC channels, and retrieves the signals (Vin, Vout, I, Trip out) from the sensors of the SSPC channels. In the present case, a microcontroller issues a two-state command, depending on whether the SSPC channel power member is to be open or closed. In the case where a microcontroller is sufficient to control all the SSPC channels, there remains a risk of loss of all SSPC channels in case of failure of this microcontroller. It is therefore necessary, in such a case, to have at least two microcontrollers (1a, 1b), each microcontroller being able to control all of the SSPC channels. This observation can be extended to a multi-microcontroller system, each microcontroller controlling a group of 25 SSPC channels. In order not to lose a group of SSPC channels due to the failure of the control microcontroller, it is necessary to have redundancy of each microcontroller controlling a group of SSPC channels. Thus, for a set of channels requiring the processing capacity of n microcontrollers, there are 2n 30 microcontrollers so that each microcontroller has the redundancy of another microcontroller dedicated to the management of the same group of SSPC channels. However, since two microcontrollers simultaneously transmit commands to the same group of 3024925 13 SSPC channels, it is necessary that a means for determining the command to be transmitted determines which control commands must be transmitted to the SSPC channel. , so that only one microcontroller remains master of the group of SSPC channels.
    [0014] The operation of the means for determining the command to be transmitted is described below. In this configuration, a group of SSPC channels comprises SSPC channels which are each linked with: the power lines (Vin, Vout); The means for determining the command to be transmitted (14, 14b, 14n); at least two microcontrollers (1a, 1b), here respectively called Master and Slave, which receive line voltage measurements, current measurements, switching information (Trip 15 out) or any other quantity necessary for the determination of the smooth operation of the SSPC route. The measurements may also include the frequency of an AC current, the distortion rate, the ripple rate of a DC power supply, and the harmonic rate of an AC power supply.
    [0015] Various structures of the control determining means to be transmitted (14, 14b, 14n) will now be described. The annotation M means that the signals come from the microcontroller the so-called Master. Conversely the annotation S means that the signals are emitted by the microcontroller lb said Slave. The master microcontroller and the slave microcontroller are each able to control the SSPC channels, the master microcontroller being considered to be the one whose orders have priority, the Slave microcontroller being considered as the redundant microcontroller ensuring the continuity of the control in the event of failure of the control. microcontroller 30 Master. However, the Master and Slave roles of microcontrollers can be exchanged during configuration. In a first embodiment illustrated in FIG. 5, the means for determining the command to be transmitted comprises four inputs connected two by two to two microcontrollers and an output intended for controlling an SSPC channel. The four inputs carry two control signals each originating from a microcontroller, denoted Cmd M and Cmd S, and two validity signals, denoted Validity M and Validity S, each also originating from a microcontroller. The means for determining the command to be transmitted 14 thus obtained comprises checking the validity of the command to ensure redundancy, while giving priority to the command received from the master controller. The input bearing the signal Cmd M and the input bearing the signal Validity M are connected to a first NAND logic gate referenced 15 (NAND acronym in English). The input carrying the signal Cmd S and the input carrying the signal Validity S are connected to a second NAND logic gate referenced 16. The input carrying the signal validity M and the second logic gate NAND referenced 16 are connected to an OR logic gate referenced 17.
    [0016] The first NAND logic gate referenced 15 and the OR logic gate referenced 17 are connected to a third NAND logic gate referenced 18. The output of the third NAND logic gate referenced 18 is connected to the output of the means of FIG. determination of the order to be transmitted 14.
    [0017] This structure is simple because it only requires two microcontrollers. The operation of this means for determining the command to be transmitted is based on the verification of the validity of the command and not on the consistency of the commands coming from at least two microcontrollers.
    [0018] The table below illustrates a truth table for this embodiment of the command determination means to be transmitted.
    [0019] 3024925 15 Cmd Master Validity Master Cmd Slave Validity Slave Cmd 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 In a second embodiment illustrated by the 6, the means for determining the command to be transmitted comprises four inputs connected in pairs to a microcontroller and an output intended for the control of an SSPC channel. The four inputs carry two control signals each from a microcontroller, denoted Cmd M and Cmd S, and two validity signals, denoted Validity M and Validity S, each also originating from a microcontroller.
    [0020] The means for determining the command to be transmitted thus obtained includes checking the validity of the command to ensure the redundancy of the command, while giving priority to the previous command in case of conflict. The input carrying the signal Cmd M and the input carrying the signal Validity M are connected to a first logic NAND gate referenced 19.
    [0021] The input bearing the signal Cmd S and the input carrying the signal validity S are connected to a second logic gate NAND referenced 20. The input carrying the signal validity M and the second logic gate NAND referenced 20 are connected to a first NOR logic gate referenced 21 The first NAND logic gate referenced 19 and the first OR logic gate referenced 21 are connected to a third NAND logic gate referenced 22.
    [0022] The input carrying the signal Cmd M and the input carrying the signal Cmd S are connected to a second exclusive OR gate referenced 23. The input carrying the signal validity M and the input carrying the signal validity S are connected to a fourth AND logic gate referenced 24. The second exclusive OR logic gate referenced 23 and the fourth AND logic gate referenced 24 are connected to a fifth AND logic gate referenced 25. The third NAND logic gate referenced 22 and the fifth gate AND logic referenced 25 are connected to a sixth NAND logic gate referenced 26. The third NAND logic gate referenced 22 is connected to a logic gate NOT referenced 27. The logic gate NOT referenced 27 and the fifth logic gate ET referenced 25 are connected to a seventh NAND logic gate referenced 28. The sixth NAND logic gate referenced 26 is connected to the first input input of an eighth logic gate NAND referenced 29.
    [0023] The seventh NAND logic gate referenced 28 is connected to the second input of a ninth NAND logic gate referenced 30. The output of the ninth NAND logic gate referenced 30 is connected to the second input of the eighth gate NAND logic referenced 29. The output of the eighth logic NAND gate 3024925 referenced 29 is connected to the first input of the ninth NAND logic gate referenced 30. The output of the eighth logic gate NAND referenced 29 is also connected to the output of the means for determining the command to be transmitted 14. This structure is close to that of the first embodiment. The advantage of this second embodiment lies in the control of the state of the order in case of conflict orders received deemed valid.
    [0024] The table below illustrates a truth table for this embodiment of the command determining means to be transmitted. Cmd Master Validity Master Cmd Slave Validity Slave Cmd 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 Previous Order 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 Previous order 1 1 1 0 1 1 1 1 1 1 3024925 18 Alternatively, it is possible to associating more than two microcontrollers to generate the control of the SSPC channels by means of a means for determining the command to be transmitted. Figure 7 illustrates an SSPC control and protection architecture using three microcontrollers. In the context of this architecture, a means for determining the command to be transmitted (14, 14b, 14n) is used to manage three commands from three different microprocessors (1a, 1b, 1c). The rest of the control architecture corresponds to the architecture illustrated in FIG. 4 and 10 described above. Such an embodiment of the means for determining the command to be transmitted is illustrated in FIG. 8. It can be seen that the means for determining the command to be transmitted comprises three inputs each connected to a microcontroller and an output intended for controlling the control. an SSPC route.
    [0025] In this example, the three microcontrollers emit commands Cmdl, Cmd2, and Cmd3, respectively. The signal Cmd transmitted at the output of the means for determining the command to be transmitted corresponds to the signal mainly received on the three inputs Cmdl, Cmd2, Cmd3.
    [0026] The input carrying the control signal Cmdl is connected to a logic gate NOT referenced 31. The input carrying the control signal Cmd2 and the input carrying the control signal Cmd3 are connected to a first logic AND gate referenced 32.
    [0027] The logic gate NOT referenced 31 and the first AND logic gate referenced 32 are connected to a second AND logic gate referenced 33. The input carrying the control signal Cmd2 and the input carrying the control signal Cmd3 are connected to a first OR gate 30 referenced 34. The input carrying the control signal Cmdl and the first logic gate OR referenced 34 are connected to a third AND logic gate referenced 35.
    [0028] The second AND logic gate referenced 33 and the third AND logic gate referenced 35 are connected to a second OR logic gate referenced 36. The table below illustrates a truth table for this embodiment of the means for determining the command to be transmitted. Cmdl Cmd2 Cmd3 Cmd 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 This control architecture and the means for determining the command to be transmitted Correspondents are used for the 10 flight commands that require the highest level of security and availability. This is achieved at the cost of using three microcontrollers. Furthermore, it is possible to use an FPGA (acronym for "field-programmable gate array", gate network 15 programmable in situ) or more generally a PLD (acronym for "Programmable Logic Device" programmable logic circuit) associated with the microcontroller. This FPGA makes it possible to lighten the load of the microcontroller by realizing part of the functions that normally fall on it. For example, it can perform digital data processing, analog data processing by interfacing with one or more ADCs (Analog-to-Digital Converter); the storage of data RAM; Etc. The FPGA can exchange data with the microcontroller 25 via parallel buses, serial or discrete signals. FIG. 9 illustrates such an embodiment, corresponding to that illustrated in FIG. 4, supplemented by two FPGAs 37a, 37b each connected between an SSPC channel and a microcontroller. 5
    权利要求:
    Claims (11)
    [0001]
    REVENDICATIONS1. Control system, particularly for an aircraft, of at least one power unit (5, 5b, 5n) able to open or close the connection between at least one source of electrical energy and at least one powered device, and means for measurement of the state of the power supply channel, the system being characterized in that it comprises at least two microcontrollers (la, lb), each capable of transmitting a command to each power unit (5, 5b , 5n) of a power supply path, and connected to at least a part of the means for measuring the state of the power supply path, a means for determining the command to be transmitted (14, 14b, 14n ) able to determine the command to be transmitted to each power unit (5, 5b, 5n) among the commands issued by each microcontroller (la, lb) to said power member (5, 5b, 5n).
    [0002]
    The system of claim 1, wherein the means for determining the command to be transmitted (14, 14b, 14n) comprises three inputs carrying a control signal from three microcontrollers, the input carrying the control signal of a first microcontroller (1a) being connected to a logic gate NO (31), the input carrying the control signal of a second microcontroller (1b) and the input carrying the control signal of a third microcontroller (1c) being connected to a first AND logic gate (32), the NO logic gate (31) and the first AND logic gate (32) being connected to a second AND logic gate (33), the input carrying the control signal of the second microcontroller (Ib) and the input carrying the control signal of the third microcontroller (1c) being connected to a first OR logic gate (34), the input carrying the control signal of the first microcontroller (1a) and the first gate logical OR (34) being connected to a third AND logic gate (35), the second AND logic gate (33) and the third AND logic gate (35) being connected to a second AND logic gate (36), the output of the second AND logic gate OR (36) being connected to the output of the means for determining the command to be transmitted (14, 14b, 14n).
    [0003]
    3. The system of claim 1, wherein the means for determining the command to be transmitted (14, 14b, 14n) comprises four inputs connected in pairs to two microcontrollers (1a, 1b), the four inputs carrying two signals of each from a microcontroller, and two validity signals, each also from a microcontroller, the second microcontroller providing redundancy of the first microcontroller, the input carrying the control signal of the first microcontroller (1a) and the input carrying the validity signal of the first microcontroller (1a) being connected to a first NAND logic gate (15), the input carrying the control signal of the second microcontroller (1b) and the input bearing the validity signal the second microcontroller (1b) being connected to a second NAND logic gate (16), the input carrying the validity signal of the first microcontroller (1a) and the second port The first NAND logic (16) is connected to an OR logic gate (17), the first NAND logic gate (15) and the OR logic gate (17) being connected to a third NAND logic gate (18). ), the output of the third NAND logic gate (18) being connected to the output of the means for determining the command to be transmitted (14).
    [0004]
    4. System according to claim 1, wherein the means for determining the command to be transmitted (14, 14b, 14n) comprises four inputs connected two by two to two microcontrollers (1a, 1b), the four inputs carry two signals. each of a microcontroller, and two validity signals, each also coming from a microcontroller, the second microcontroller providing the redundancy of the first microcontroller, the input carrying the control signal of the first microcontroller (1a) and the input carrying the validity signal of the first microcontroller (1a) are connected to a first NAND logic gate (19), the input carrying the control signal of the second microcontroller (1b) and the input carrying the signal of validity of the second microcontroller (1b) are connected to a second NAND logic gate (20), the input bearing the validity signal of the first microcontroller (1a) and the second p NAND logic (20) are connected to a first OR logic gate (21), the first NAND logic gate (19) and the first OR logic gate (21) are connected to a third NAND logic gate. (22), the input carrying the control signal of the first microcontroller (1a) and the input carrying the control signal of the second microcontroller (1b) being connected to a second exclusive OR gate (23), the input carrying the validity signal of the first microcontroller (1a) and the input bearing the validity signal of the second microcontroller (1b) being connected to a fourth AND logic gate (24), the second exclusive OR logic gate (23) and the fourth AND logic gate (24) being connected to a fifth AND logic gate (25), the third NAND logic gate (22) and the fifth AND logic gate (25) being connected to a sixth AND logic gate 3024925 24 (26), the third logical gate NAND (22) both connected to a logic gate NO (27), the logic gate NO (27) and the fifth logic gate AND (25) being connected to a seventh logic gate NAND (28), the sixth logic gate NAND ( 26) being connected to the first input of an eighth NAND logic gate (29), the seventh NAND logic gate (28) being connected to the second input of a ninth NAND logic gate (30), the output of the ninth NAND logic gate (30) being connected to the second input of the eighth NAND logic gate (29), the output of the eighth NAND logic gate (29) being connected to the first input of the ninth NAND logic gate (30), the output of the eighth NAND logic gate (29) also being connected to the output of the command determining means to be transmitted (14).
    [0005]
    5. Use of the system according to any one of the preceding claims, in an electrical distribution system of an aircraft comprising at least one power supply channel comprising at least one power member (5, 5b, 5n). 20
    [0006]
    6. A control method, particularly for an aircraft, of a power unit (5, 5b, 5n) able to open or close the connection between at least one source of electrical energy and at least one powered device, by means of a control system comprising means for measuring the state of the connection 25 at least two microcontrollers (la, lb) each able to issue a command to each power member (5, 5b, 5n), and connected to at least a part of the means for measuring the state of the connection, characterized in that it comprises a step in the course of which the control transmitted to each power unit (5, 5b, 5n) is determined among the commands issued by the microcontrollers to each power unit (5, 5b, 5n). 3024925 25
    [0007]
    The method according to claim 6, wherein an output corresponding to the command received from a majority of the microcontrollers (1a, 1b, 1c) is output, the control system comprising an odd number of microcontrollers (1a, 1b, 1c) greater than three.
    [0008]
    The method of claim 6, wherein each microcontroller (1a, 1b) issues a command that can take a first value or a second value and a validity value that can take a first value if the command is judged valid by the microcontroller and a second value if the command is considered invalid by the microcontroller, A second microcontroller ensuring the redundancy of the first microcontroller, If the commands received as inputs are accompanied by 15 different validity values, the received command input is transmitted for which the value of validity corresponds to the first value, Or, if different commands received as entries are accompanied by validity values corresponding to the second validity value, the first command value is transmitted, Or, if identical commands received as inputs are accompanied Validity values correspond to the second value of vali In this case, the first command value is transmitted.
    [0009]
    The method of claim 8, wherein if different commands received as inputs are accompanied by validity values corresponding to the first value, the command transmitted by the first microcontroller is transmitted.
    [0010]
    The method of claim 8, wherein if different commands received as inputs are accompanied by validity values corresponding to the first value, the previously received command is transmitted.
    [0011]
    11. Use of the method according to any one of claims 6 to 10, for the control of the electrical distribution system 3024925 26 of an aircraft comprising at least one power supply channel comprising at least one power member (5, 5b , 5n). 5
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    公开号 | 公开日
    GB201514124D0|2015-09-23|
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    BR102015019317A2|2016-02-16|
    DE102015113281A1|2016-02-18|
    US9935539B2|2018-04-03|
    FR3024925B1|2016-08-26|
    CN105373031B|2021-10-08|
    CA2898067A1|2016-02-14|
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    法律状态:
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1457843A|FR3024925B1|2014-08-14|2014-08-14|SYSTEM AND METHOD FOR CONTROLLING AT LEAST ONE POWER MEMBER, IN PARTICULAR FOR AN AIRCRAFT|FR1457843A| FR3024925B1|2014-08-14|2014-08-14|SYSTEM AND METHOD FOR CONTROLLING AT LEAST ONE POWER MEMBER, IN PARTICULAR FOR AN AIRCRAFT|
    CA2898067A| CA2898067A1|2014-08-14|2015-07-21|System and control process for at least one power device specifically for an aircraft|
    GB1514124.5A| GB2530886B|2014-08-14|2015-08-11|System and method for controlling at least one switching device, especially for use in aircraft|
    DE102015113281.8A| DE102015113281A1|2014-08-14|2015-08-12|System and method for controlling at least one power controller, in particular for an aircraft|
    BR102015019317A| BR102015019317A2|2014-08-14|2015-08-12|command system, system usage, command process, and process usage|
    CN201510502633.7A| CN105373031B|2014-08-14|2015-08-14|System and method for controlling at least one switching device, in particular for use in an aircraft|
    US14/827,098| US9935539B2|2014-08-14|2015-08-14|System and method for controlling at least one switching device, especially for use in aircraft|
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